Latch Address: This signal indiates that the bus contains a resister address which should be latched in the PSG. DA7~DA0 are in the input mode.
from 6522, ORB[0] = BC1, ORB[1] = BDIR, ORB[2] = ~RESET
ORB = 7 (111): Latch Address, sets register address
ORB = 6 (110): Write To PSG register
ORB = 4 (100): Inactive
ORB = 0~3 (0xx): Reset : clears all registers
procedure: Command -> Inactive
* sets PSG register to N (0~15)
lda #N
sta ora ; connected to psg data bus
lda #7 ; loads 'latch address' command
sta orb ; sends the command. connected to bus controls (BDIR, BC1)
lda #4 ; loads inactive command
sta orb ; sends the command
* writes data to PSG's current register
lda data
sta ora
lda #6 ; 'write to psg' command
sta orb
lda #4
sta orb
* reset
stz orb
lda #4
sta orb
==> PSG, R[2] = 2
set PSG register to 2 -> writes 2 to PSG
| Register \ bit | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | |
| R0 | Channel A Tone Period | 8-Bit Fine Tune A | |||||||
| R1 | 4-Bit Coarse Tune A | ||||||||
| R2 | Channel B Tone Period | 8-Bit Fine Tune B | |||||||
| R3 | 4-Bit Coarse Tune B | ||||||||
| R4 | Channel C Tone Period | 8-Bit Fine Tune C | |||||||
| R5 | 4-Bit Coarse Tune C | ||||||||
| R6 | Noise period | 5-Bit Period control | |||||||
| R7 | Enable ( bit 0 = on, 1 = off ) | IN/OUT | Noise | Tone | |||||
| IOB | IOA | C | B | A | C | B | A | ||
| R8 | Channel A Envelope on/off, Volume | Env | volume | ||||||
| R9 | Channel B Envelope on/off, Volume | Env | volume | ||||||
| R10 | Channel C Envelope on/off, Volume | Env | volume | ||||||
| R11 | Envelope Period | 8-Bit Fine Tune Envelope | |||||||
| R12 | 4-Bit Coarse Tune Envelope | ||||||||
| R13 | Envelope Shape/Cycle | CONT | ATT | ALT | HOLD | ||||
| R14 | I/O Port A Data Store | 8-Bit Parallel I/O on Port A | |||||||
| R15 | I/O Port B Data Store | 8-Bit Parallel I/O on Port B | |||||||
* Enable output Channel A (R7 = 0011 1110)
